1. Field of the Disclosure
The present disclosure relates to electronic devices, more particularly, to electronic devices that have heterojunction regions and process for forming them.
2. Description of the Related Art
Attempting to form improved versions of both a p-channel (“PMOS”) component and an n-channel (“NMOS”) component in a single electronic device (“complimentary metal-oxide-semiconductor” or “CMOS”) can be far more difficult and costly than improving either component alone. Individual component performance can be improved by selection and engineering of channel materials, electrode work functions, gate materials, implant doses, and the like. However, in general, improvement in performance for one type of transistor tends to degrade the performance of the other type of transistor. Thus, substantially any over all improvement in CMOS performance tends to require inclusion of the separate improvements of both the PMOS and NMOS components.
For example, a substrate surface, as obtained from a commercially-available source, normally supports one transistor type. In order to form both a p-channel transistor and an n-channel transistor along the substrate surface, a second region of the substrate that supports the other transistor type can be formed adding expense to the process. One method is to remove and replace portions of the substrate, or if the substrate is a silicon-on-insulator substrate, expose a portion of the base layer. Still another method is to deposit a SiGe layer that is over a micron thick over the substrate. However, such methods require long processes be used that are both time consuming and expensive to perform. Long etch processes can be required to avoid the n-channel transistor and the p-channel transistor being formed at substantially different elevations, which adds complexity to both imaging and planarization processing during manufacturing.
Another challenge is reducing the switching time so an electronic component can be used in a higher performance electronic device. One attempt is to match the work function of the gate electrode with the appropriate energy band for the channel region to lower the threshold voltage (“Vth”) of the electronic component. For example, a high performance n-channel transistor has a gate electrode work function closer to the conduction band than the valence band of the n-channel region, and a high performance p-channel transistor has a work function closer to the valence band than the conduction band of the p-channel region. However, this requires that a gate electrode with the appropriate work function be formed for each of the channel region types.
In an attempt to reduce manufacturing costs, a single gate electrode can be used, however either the n-channel transistor, the p-channel transistor, or the combination thereof will have a worse mismatch and therefore a higher Vth than the case with two different gate electrode work functions. In a further attempt to use a single gate electrode process, one or both of the channel regions can be lightly doped or counter doped. However, the centroid of the distribution of subthreshold carriers within a lightly doped or counter doped channel can be farther from the channel surface leading to an increase in undesirable buried channel effects.
Another attempt to improve performance is to move the source and drain regions closer to each other. However, electrical field effects from a drain region, such as drain induced barrier lowering, affect a portion of the channel region adjacent to the drain and scale with the operating voltage rather than physical dimension. Thus, unless the operating voltage is scaled down as the channel region is scaled down, such a portion accounts for a higher percentage of the total channel region and the leakage increases accordingly.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention. The use of the same reference symbols in different drawings indicates similar or identical items.